Volatile semiconductor memories, such as dynamic random access memories (DRAMs) requiring a refresh operation to retain data and static random access memories (SRAMs), and non-volatile semiconductor memories use sense amplifiers. Generally, a dynamic type latch circuit using a CMOS cross-coupled latch is employed in these sense amplifiers. When data is selectively read from a sense amplifier selected by a column address to a data bus (termed common data line) or when data from the common data line is selectively written, a selected column switch, responsive to a column selection signal supplied thereto, is set to be electrically conductive. This column switch includes nMOS transistors each having a gate supplied with a column selection signal (YS) outputted from a column decoder. The following description outlines a sense amplifier and a column switch of related arts.
<Sense Amplifier 1>
FIG. 4 is a diagram illustrating a circuit configuration of a typical example of a sense amplifier. As illustrated in FIG. 4, which is also referred to in the description of examples of the present invention, a sense amplifier (SA) using a CMOS cross-coupled latch includes nMOS transistors 43 and 44 having sources commonly coupled to a first common source line NCS; and pMOS transistors 45 and 46 having sources commonly coupled to a second common source line PCS and having drains connected to drains of the nMOS transistors 43 and 44, respectively. Gates of the nMOS transistor 44 and the pMOS transistor 46 are connected to a bit line BL, which is one of a bit line pair BL and /BL. It is noted that BL and /BL indicate “True” and “Bar” bit lines which may be designated as BLT and BLB, respectively. The bit line BL is also connected to a connection node of drains of the nMOS transistor 43 and the pMOS transistor 45. Gates of the nMOS transistor 43 and the pMOS transistor 45 are connected to the bit line /BL, which is the other one of the bit line pair BL and /BL. The bit line /BL is also connected to a connection node of drains of the nMOS transistor 44 and the pMOS transistor 46. In reading data from a memory cell, when the bit line pair BL and /BL are brought to High and Low levels, respectively, the nMOS transistor 44 and the pMOS transistor 45 are turned electrically conductive (ON) and the pMOS transistor 46 and the nMOS transistor 43 are turned electrically non-conductive (OFF). As a result, the bit line pair BL and /BL are brought to potentials of the second common source line PCS and the first common source line NCS, respectively (namely, a potential difference between the bit line pair BL and /BL is amplified and latched). When the bit line pair BL and /BL are brought to Low and High levels, respectively, the pMOS transistor 46 and the nMOS transistor 43 are turned electrically conductive and the nMOS transistor 44 and the pMOS transistor 45 are turned electrically non-conductive. As a result, the bit lines pair /BL and BL are brought to potentials of the second common source line PCS and the first common source line NCS, respectively (namely, a potential difference between the bit line pair BL and /BL is amplified and latched).
<Sense Amplifier 2>
Other than the above sense amplifier 1, another example of the sense amplifier includes a latch circuit (not illustrated) that senses memory cell information by using a sensing circuit (not illustrated) and that holds the sensed data in a volatile manner. In this case, whether this latch circuit has the above sensing capabilities is not an issue. This type of latch circuit will also be referred to as a sense amplifier herein as needed.
<Column Switch>
As illustrated in FIG. 4, a column switch (CSW) includes an nMOS transistor 41 having a source connected to the bit line BL, a gate connected to a column selection signal YS, and a drain connected to a common data line CDL, and an nMOS transistor 42 having a source connected to the bit line /BL, a gate connected to the column selection signal YS, and a drain connected to a common data line /CDL. The column switch (CSW) is arranged for each sense amplifier SA. The column switch (CSW) including an nMOS transistor may be also termed as nMOS column switch. As will be described below, a common data line pair (data bus) CDL and /CDL is arranged in common for a plurality of bit line pairs, and the sense amplifier (SA) is connected to the common data line pair CDL and /CDL via a column switch (CSW) which is turned electrically conductive by the column selection signal YS from a column decoder (not shown in FIG. 4).
Patent Document 1:
    Japanese Patent Kokai Publication No. JP-H11-162170A, which corresponds to U.S. Pat. No. 6,061,295A
The following analysis is given by the present invention. With continued shrinking of MOS transistor dimensions, random variations in a threshold voltage (Vt) of MOS transistors forming a CMOS cross-coupled latch in a sense amplifier and an nMOS transistor forming a column switch are increased. Thus, when the nMOS transistor forming a column switch is turned electrically conductive (ON), a noise margin with respect to capability of the sense amplifier to retain sensed data in a volatile manner is decreased.
Referring to FIG. 4, assuming that both of the common data line pair CDL and /CDL are pre-charged and equalized to a High potential and the bit line pair BL and /BL, to which memory cell data has been read, are set to High and Low levels, respectively, if the nMOS transistors 41 and 42 each forming the column switch CSW are turned electrically conductive, the bit line BL and the common data line CDL are electrically connected, and the bit line /BL and the common data line /CDL are electrically connected. Electric-charge redistribution occurs between the pre-charged common data line /CDL (High level) and the bit line /BL (Low level). Since capacitance (parasitic capacitance) of the common data line is larger than that of the bit line, as a result of the electric-charge redistribution, the potential of the bit line /BL is raised from a Low level. In case the nMOS transistor 43 has a relatively low threshold voltage (Vt), when a potential of the bit line /BL exceeds the threshold voltage (Vt) of the nMOS transistor 43, the nMOS transistor 43 changes from a non-conductive state (OFF state) to a conductive state (ON state). As a result, the bit line BL is electrically connected to the source common line NCS via the nMOS transistor 43 which is turned electrically conductive and the potential of the bit line BL is decreased from a High level to a Low level. Consequently, the pMOS transistor 46 changes from a non-conductive state to a conductive state, the bit line /BL is connected to the common source line PCS via the pMOS transistor 46 which is turned electrically conductive and the potential of the bit line /BL is raised to a High level. The fact that the nMOS transistor 44 and the pMOS transistor 45 have changed from a conductive state to a non-conductive state indicates that data latched by the sense amplifier (SA) has been inverted.
The lowering of an operating voltage of a sense amplifier, resulting from the advancement of miniaturization in semiconductor processing and reduction of a power supply voltage, may further decrease a noise margin of the sense amplifier.
As a result, it is becoming increasingly difficult to reconcile ensuring a noise margin of a sense amplifier to have a sufficient signal amount of the common data line (data bus) in a read operation and increasing a write speed in a write operation.
More specifically, for example, in order to increase the write speed in a write operation, the semiconductor device is required to have some means or control method for quickly inverting a sense amplifier retaining data corresponding to cell data of a memory cell, a value of which is opposite (or complementary) to that of write data supplied to common data line pair. However, on the other hand, if the sense amplifier should be adapted to be able to be inverted at high speed by the means or control method, data latched by the sense amplifier may be easily inverted by a noise generated in a read operation, thus resulting in a decrease of the noise margin of the sense amplifier that operates at a low voltage. Namely, the means or control method above described is, so to speak, a double-edged sword.
<Patent Document 1>
Patent Document 1 found through a related art search conducted by the applicant discloses a semiconductor memory device including a clock buffer generating a control signal in response to a clock signal; a column selection signal control unit generating a column selection control signal in response to the control signal and a column address enable signal that controls a column address signal in a read access and generating a column selection control signal which is delayed by a certain time from the column selection control signal generated in reading, in response to the control signal, the column address enable signal, and a write control signal in a write access; a column decoder generating a column selection signal in response to the column selection control signal and the column address signal; and a column selection gate sending data externally supplied to a sense amplifier in response to the column selection signal and sending data outputted from a sense amplifier to the outside. According to Patent Document 1, a YS signal activation timing is varied depending on reading or writing, so that activation of the YS signal in a write operation is delayed, as compared with activation of the YS signal in a read operation. Consequently, the substantive write time can be extended, and the write operating margin can be improved.
The above configuration of Patent Document 1 cannot solve the problem of reduction of the noise margin of a sense amplifier operating at a low voltage in a read operation.